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PMC51x LoRa Module Specification ​

PMC51x is a Mini-PCIe LoRa module used as the LoRa radio component of the GD6 series LoRaWAN gateways. This document describes its functions, technical specifications, pin definitions, interface requirements, and model selection.

1. Product Overview ​

1.1 Positioning and GD6 Relationship ​

PMC51x is the LoRa radio component of GD6 and connects to the host through a Mini-PCIe form factor. It is based on the Semtech SX1302 LoRa baseband chip, with a pin-compatible SX1303 option available for project customization. The module operates in half-duplex mode, communicates with the host over SPI, and supports the Semtech open-source Packet Forwarder.

The final digit in PMC514 and PMC518 identifies the radio-frequency family; it does not indicate the number of LoRaWAN channels:

  • PMC514: 400 MHz family, including EU433 and CN470.
  • PMC518: 800 MHz and higher family, including EU868, AS923, AU915, US915, and KR920.

1.2 Key Features ​

  • Standard Mini-PCIe form factor for straightforward integration and replacement.
  • SX1302 baseband with a customizable pin-compatible SX1303 option.
  • SPI host interface and PPS timing input.
  • EU433, CN470, EU868, AS923, AU915, US915, and KR920 regional standards.
  • First-generation I-PEX antenna connector.
  • Eight parallel receive paths with SF5–SF12 support.
  • Receive sensitivity down to -141 dBm.
  • One transmit path with up to 22 dBm output power.
  • Built-in power-on reset sequencing to simplify host control.

2. Product Views ​

2.1 Front View ​

PMC51x module front view

2.2 Bottom View ​

PMC51x module bottom view

3. Technical Specifications ​

3.1 Electrical and Mechanical Specifications ​

ItemSpecification
Form factorMini-PCIe
Dimensions30.0 mm × 51.0 mm × 4.5 mm
Host interfaceSPI
Operating modeHalf-duplex
Supply voltageDC 3.3–5 V
Transmit current< 120 mA
Receive current< 60 mA
Operating temperature-40 to +85 °C
Antenna connectorFirst-generation I-PEX

3.2 Radio Specifications ​

ItemSpecification
Baseband chipSX1302; customizable pin-compatible SX1303
Receive paths8
Transmit paths1
Spreading factorsSF5–SF12
Receive sensitivityDown to -141 dBm
Maximum transmit power22 dBm
EU433433–434 MHz
CN470470–510 MHz
EU868863–870 MHz
AS923920–928 MHz
AU915915–928 MHz
US915902–928 MHz
KR920Configured according to KR920 regional parameters

4. Mini-PCIe Pin Definition ​

4.1 Signal Types ​

AbbreviationMeaning
PIPower input
DIDigital input
DODigital output
IOBidirectional digital signal
NCNot internally connected
RESERVEDReserved signal

4.2 Main Pins ​

FunctionPinsDescription
GND4, 9, 15, 18, 21, 26, 27, 29, 34, 35, 37, 40, 43, 50Power ground
VCC_3V32, 24, 39, 41, 52Power input
PPS19GPS PPS timing input
NRESET22Module reset, active high
RX_ON42Receive-state output connected to the onboard indicator
TX_ON44Transmit-state output connected to the onboard indicator
SX_SCK45SPI clock input
CFG_ON46Configuration-state output connected to the onboard indicator
SX_MISO47SPI data output
SX_MOSI49SPI data input
SX_CSN51SPI chip-select input

4.3 Complete 52-Pin Definition ​

PinMini-PCIe NameModule SignalTypeDescription
1WAKE#RESERVEDDOReserved for pass-through variants; leave floating
23.3VauxVCC_3V3PIPower input
3COEX1NC—Not internally connected; leave floating
4GNDGND—Power ground
5COEX2NC—Not internally connected; leave floating
61.5VNC—Not used
7CLKREQ#NC—Not internally connected; leave floating
8UIM_PWRNC—Not used
9GNDGND—Power ground
10UIM_DATARESERVEDIOReserved for pass-through variants; leave floating
11REFCLK-RESERVEDDIReserved for pass-through variants; leave floating
12UIM_CLKRESERVEDIOReserved for pass-through variants; leave floating
13REFCLK+RESERVEDDOReserved for pass-through variants; leave floating
14UIM_RESETNC—Not used
15GNDGND—Power ground
16UIM_VPPNC—Not internally connected; leave floating
17RESERVEDNC—Not internally connected; leave floating
18GNDGND—Power ground
19RESERVEDPPSDIGPS PPS timing input; may be left floating when unused
20W_DISABLE#NC—Not internally connected; leave floating
21GNDGND—Power ground
22PERST#NRESETDIReset control, active high
23PERn0RESERVEDDIReserved; leave floating
243.3VauxVCC_3V3PIPower input
25PERp0NC—Not used
26GNDGND—Power ground
27GNDGND—Power ground
281.5VNC—Not used
29GNDGND—Power ground
30SMB_CLKNC—Not internally connected; leave floating
31PETn0RESERVEDDOReserved; leave floating
32SMB_DATANC—Not internally connected; leave floating
33PETp0NC—Not used
34GNDGND—Power ground
35GNDGND—Power ground
36USB_D-RESERVEDIOReserved for pass-through variants; leave floating
37GNDGND—Power ground
38USB_D+RESERVEDIOReserved for pass-through variants; leave floating
393.3VauxVCC_3V3PIPower input
40GNDGND—Power ground
413.3VauxVCC_3V3PIPower input
42LED_WWAN#RX_ONDOReceive-state indicator connected to the onboard LED
43GNDGND—Power ground
44LED_WLAN#TX_ONDOTransmit-state indicator connected to the onboard LED
45RESERVEDSX_SCKDISPI clock input
46LED_WPAN#CFG_ONDOConfiguration-state indicator connected to the onboard LED
47RESERVEDSX_MISODOSPI data output
481.5VNC—Not used
49RESERVEDSX_MOSIDISPI data input
50GNDGND—Power ground
51RESERVEDSX_CSNDISPI chip-select input
523.3VauxVCC_3V3PIPower input

5. Interface Details ​

5.1 Power Interface ​

The module is powered through the Mini-PCIe VCC_3V3 pins and operates from DC 3.3–5 V. The host must provide a stable supply with enough headroom for the transmit peak current and should place decoupling capacitors close to the module. All GND pins must be connected reliably.

5.2 SPI Interface ​

The SPI signals are SX_SCK, SX_MISO, SX_MOSI, and SX_CSN. The host SPI controller must support full-duplex communication. Refer to the Semtech SX1302 data sheet for timing, electrical limits, and register-access procedures.

5.3 Control and Status Interfaces ​

SignalDirectionFunction
PPSInputExternal GPS PPS timing
NRESETInputModule reset, active high
RX_ONOutputReceive operating state
TX_ONOutputTransmit operating state
CFG_ONOutputConfiguration operating state

6. Signal Behavior ​

6.1 PPS ​

The PPS pin accepts a one-pulse-per-second signal from a GPS module so that packets can carry precise timestamps. The pin may be left floating when PPS is not used.

6.2 NRESET ​

To reset the module, drive NRESET high for 0.05–0.2 s and then release it. Keep the reset trace short and shield it with an adjacent ground trace where practical to reduce the risk of unintended resets.

6.3 RX_ON, TX_ON, and CFG_ON ​

RX_ON is high while the module is receiving, TX_ON is high while it is transmitting, and CFG_ON indicates the configuration state. These signals are connected to onboard LEDs and are associated with SX1302 GPIOs.

7. Antenna Interface ​

The module uses a first-generation I-PEX antenna receptacle. Use a matching RF cable and antenna, and ensure that the antenna band matches the module model and deployment region. The RF routing and mechanical design should avoid applying lateral stress to the connector.

First-generation I-PEX receptacle dimensions and recommended footprint

8. Models and Regional Standards ​

ModelFrequency FamilySupported Regional Standards
PMC514-433-N400 MHzEU433
PMC514-470-N400 MHzCN470
PMC518-868-N800 MHz and higherEU868
PMC518-915-N800 MHz and higherAS923, AU915, US915, KR920

Select a model and regional configuration that comply with local regulations. The "4" or "8" in the model family identifies its frequency range; it does not indicate the number of receive or transmit channels.

9. Integration and Safety Notes ​

  • Disconnect power before installing or removing the module.
  • Apply ESD precautions and avoid touching RF components or the edge connector directly.
  • Connect the correct antenna before transmission and verify that its band and impedance match the module.
  • Do not use NC or RESERVED pins for undocumented functions.
  • Ensure the host enclosure keeps the module within its -40 to +85 °C operating range.
  • The final product's radio parameters, transmit power, and deployment region must meet applicable regulations and certification requirements.

10. Contact ​

11. Manual Downloads ​